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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . s y n c h r o n o u s b u c k p w m c o n t r o l l e r the APW7064 uses fixed 200khz switching frequency, voltage mode, synchronous pwm controller which drives dual n-channel mosfets. the device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under- voltage protection. the APW7064 provides excellent regulation for output load variation. the internal 1.2v temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. an built-in digital soft- start with fixed soft-start interval prevents the output voltage from overshoot as well as limiting the input current. the APW7064 with excellent protection functions: por and uvp. the power-on-reset (por) circuit can monitor v cc supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides output with controlled voltage rise. the under- voltage protection (uvp) monitors the voltage of fb pin for short-circuit protection. when the v fb is less than 50% of v ref (0.6v), the controller will shutdown the ic directly. f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s single 12v power supply required fast transient response - 0~90% duty ratio 1.2v reference with 1% accuracy shutdown function by controlling comp pin voltage internal soft-start (5.1ms) function voltage mode pwm control design under-voltage protection 200khz fixed switching frequency sop-8p package lead free and green devices available (rohs compliant) graphics card mother board smps t y p i c a l a p p l i c a t i o n c i r c u i t p i n c o n f i g u r a t i o n 7 comp ugate 2 gnd 3 lgate 4 6 fb 5 vcc 8 phase boot 1 sop-8p APW7064 = thermal pad (connected to gnd plane for better heat dissipation) v out 12v v in APW7064 l
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n symbol parameter rating unit v cc vcc to gnd - 0.3 to +16 v v boot boot to phase - 0.3 to +16 v v ugate ugate to phase <400ns pulse width >400ns pulse width - 5 to v boot +5 - 0.3 to v boot +0.3 v v lgate lgate to p gnd <400ns pulse width >400ns pulse width - 5 to v cc +5 - 0.3 to v cc +0.3 v v phase phase to gnd < 2 00ns pulse width > 2 00ns pulse width - 10 to + 30 - 2 to 16 v v comp, v fb comp , fb to gnd - 0.3 to + 7 t j junction temperature range - 20 ~ 150 c t stg st orage temperature - 65 ~ 150 c t sdr maximum lead soldering temperature, 10 seconds 260 c note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in f ree a ir sop - 8p 80 o c/w n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . APW7064 handling code temperature range package code APW7064 ka : APW7064 xxxxx assembly material xxxxx - date code package code ka : sop-8p temperature range e : -20 to 70 o c handling code tr : tape & reel assembly material g : halogen and lead free device note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s symbol parameter rating unit v cc v cc supply voltage 10.8 to 13.2 v v out converter output voltage 1.2 to 5 v v in converter input voltage 2. 9 to 13.2 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 3 r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( c o n t . ) symbol parameter rating unit i out converter output current 0 to 3 0 a t a ambient temperature range - 20 to 70 c t j junction temperature range - 2 0 to 125 c e l e c t r i c a l c h a r a c t e r i s t i c s u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . APW7064 symbol parameter test conditions min . typ . max . unit supply current i vcc vcc nominal supply current ugate and lgate open - 5 10 ma vcc shutdown supply current ugate, lgate = gnd - 1 2 ma power - on - reset rising vcc threshold 9 9.5 10 v falling vcc threshold 7.5 8 8.5 v comp shutdown threshold - 1.2 - v comp shutdown hysteresis - 0.1 - v oscillator f osc free running frequency 170 200 230 khz d v osc ramp amplitude - 1. 6 - v p - p reference voltage v ref reference voltage measured at fb pin - 1.2 - v accuracy t a = - 20~70 c - 1 .0 - + 1 .0 % e rr or amplifier gain open loop gain r l =10k, c l =10p f (note 3 ) - 8 8 - db gbwp open loop bandwidth r l =10k, c l =10p f (note 3 ) - 15 - mhz sr slew rate r l =10k, c l =10p f (note 3 ) - 6 - v/ m s fb input c urrent v fb = 0.8v (note 3 ) - 0.1 1 m a v comp comp high voltage - 5.5 - v v comp comp low voltage - 0 - v i comp comp source current v comp =2v - 5 - ma i comp comp sink current v comp =2v - 5 - ma gate drivers i ugate upper gate source current - 2.6 - a i ugate upper gate s ink current v boot = 12 v, v ugate - v phase = 2 v v boot = 12 v, v ugate - v phase = 2 v - 1.05 - a i l gate low er gate source current - 4.9 - a i lgate low er gate s ink current v cc = 12 v, v l gate = 2 v v cc = 12 v, v l gate = 2 v - 1.4 - a r ugate upper ga te s ource impedance v boot = 12v, i ugate = 0. 1 a - 2 3 w r ugate upper gate sink impedance v boot = 12v, i ugate = 0. 1 a - 1.6 2.4 w r l gate low er gate source impedance v cc = 12v, i l gate = 0. 1 a - 1.3 1.95 w
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v , a n d t a = - 2 0 ~ 7 0 c . t y p i c a l v a l u e s a r e a t t a = 2 5 c . APW7064 symbol parameter test conditions min . typ . max . unit gate drivers (cont.) r lgate lower gate sink impedance v cc = 12v, i l gate = 0. 1 a - 1.25 1.8 8 w t d dead time - 20 - ns protections v uvp under - voltage threshold trip point percent of v ref 45 50 55 % soft - start t ss soft - start interval 4.4 5.1 6 m s note 3 : guaranteed by design.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 5 0 1 2 3 4 5 6 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ugate source current (a) u g a t e v o l t a g e ( v ) u g a t e s o u r c e c u r r e n t v s . u g a t e v o l t a g e ugate sink current (a) u g a t e v o l t a g e ( v ) u g a t e s i n k c u r r e n t v s . u g a t e v o l t a g e lgate source current (a) l g a t e v o l t a g e ( v ) l g a t e s o u r c e c u r r e n t v s . l g a t e v o l t a g e lgate sink current (a) l g a t e v o l t a g e ( v ) l g a t e s i n k c u r r e n t v s . l g a t e v o l t a g e switching frequency (khz) j u n c t i o n t e m p e r a t u r e ( c ) s w i t c h i n g f r e q u e n c y v s . j u n c t i o n t e m p e r a t u r e v boot =12v v phase =2v v cc =12v reference voltage (v) j u n c t i o n t e m p e r a t u r e ( c ) r e f e r e n c e v o l t a g e v s . j u n c t i o n t e m p e r a t u r e v boot =12v v phase =2v 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 185 188 191 194 197 200 203 206 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 1.188 1.19 1.192 1.194 1.196 1.198 1.2 1.202 1.204 v cc =12v v cc =12v v cc =12v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s p o w e r o n p o w e r o f f 1 1 2 2 1 1 2 2 3 3 3 3 e n ( e n = v c c ) s h u t d o w n ( e n = g n d ) 1 1 2 2 1 1 2 2 c h 1 : v c o m p ( 1 v / d i v ) c h 2 : v o u t ( 2 v / d i v ) c h 3 : u g a t e ( 2 0 v / d i v ) c h 4 : l g a t e ( 1 0 v d i v ) t i m e : 5 m s / d i v 3 3 3 3 c h 1 : v c c ( 5 v / d i v ) c h 2 : v f b ( 1 v / d i v ) c h 3 : v o u t ( 2 v / d i v ) c h 4 : u g a t e ( 2 0 v d i v ) t i m e : 1 0 m s / d i v c h 1 : v c o m p ( 1 v / d i v ) c h 2 : v o u t ( 2 v / d i v ) c h 3 : u g a t e ( 2 0 v / d i v ) c h 4 : l g a t e ( 1 0 v d i v ) t i m e : 5 m s / d i v c h 1 : v c c ( 5 v / d i v ) c h 2 : v f b ( 1 v / d i v ) c h 3 : v o u t ( 2 v / d i v ) c h 4 : u g a t e ( 2 0 v d i v ) t i m e : 1 0 m s / d i v 4 4 4 4 v cc =12v, v in =12v v out =3.3v, l=1uh v cc =12v, v in =12v v out =3.3v, l=1uh 4 4 4 4 v cc =12v, v in =12v v out =3.3v, l=1uh v cc =12v, v in =12v v out =3.3v, l=1uh
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s ( c o n t . ) u g a t e r i s i n g u g a t e f a l l i n g 1 1 2 2 1 1 2 2 3 3 3 3 l o a d t r a n s i e n t r e s p o n s e u n d e r v o l t a g e p r o t e c t i o n 1 1 2 2 1 1 2 2 3 3 4 4 c h 1 : u g a t e ( 2 0 v / d i v ) c h 2 : l g a t e ( 5 v / d i v ) c h 3 : v p h a s e ( 1 0 v / d i v ) t i m e : 5 0 n s / d i v c h 1 : v o u t ( 2 0 0 m v / d i v ) c h 2 : i o u t ( 5 a / d i v ) t i m e : 1 m s / d i v c h 1 : u g a t e ( 2 0 v / d i v ) c h 2 : l g a t e ( 5 v / d i v ) c h 3 : v p h a s e ( 1 0 v / d i v ) t i m e : 5 0 n s / d i v c h 1 : i o u t ( 1 0 a / d i v ) c h 2 : v f b ( 1 v / d i v ) c h 3 : u g a t e ( 2 0 v / d i v ) c h 4 : l g a t e ( 1 0 v / d i v ) t i m e : 1 m s / d i v v cc =12v, v in =12v v out =3.3v, l=1uh v cc =12v, v in =12v v out =3.3v, l=1uh v cc =12v, v in =12v v out =3.3v, l=1uh v cc =12v, v in =12v v out =3.3v, l=1uh
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 8 o p e r a t i n g w a v e f o r m s ( c o n t . ) s h o r t t e s t 1 1 2 2 3 3 c h 1 : v o u t ( 2 v / d i v ) c h 2 : u g a t e ( 2 0 v / d i v ) c h 3 : l g a t e ( 1 0 v / d i v ) t i m e : 2 m s / d i v v cc =12v, v in =12v v out =3.3v, l=1uh p i n d e s c r i p t i o n pin no. name function 1 boot a bootstrap circuit with a diode connected to vcc is used to create a voltage suitable to drive a logic - level n - channel mosfet. 2 ugate connect this pin to the high - side n - channel mosfet gate. this pin provides gate drive f or the high - side mosfet. 3 gnd the gnd terminal provides return path for the ic bias current and the low - side mosfet driver pull - low current. connect the pin to the system ground via very low impedance layout on pcbs. 4 lgate connect this pin to the low - side n - channel mosfet gate. this pin provides gate drive for the low - side mosfet. 5 vcc connect this pin to a 12v supply voltage. this pin provides bias supply for the control circuitry and the low - side mosfet driver. the voltage at this pin is monitored for the power - on - reset (por) purpose. it is recommended that a decoupling capacitor (1 to 10 m f) be connected to gnd for noise decoupling. 6 fb this pin is the inverting input of the internal error amplifier. connect this pin to the output (v out ) of the converter via an external resistor divider for closed - loop operation. the output voltage set b y the resistor divider is determined using the following formula: ? ? ? ? ? + = gnd out out r r 1 2 . 1 v where r out is the resistor connected from v out to fb, and r gnd is the resistor connected from fb to gnd. the fb pin is also monitored for under voltage events. 7 com p this pin is the output of pwm error amplifier. it is used to set the compensation components. in addition, if the pin is pulled below 1.2v, it will disable the device. 8 phase this pin is the return path for the upper gate driver. connect this pin to th e upper mosfet source.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 9 b l o c k d i a g r a m t y p i c a l a p p l i c a t i o n c i r c u i t v out 2200 m fx2 vcc boot ugate phase lgate gnd fb 12v v in comp 0.1 m f apm2509 apm2506 1 m f 10 m f 1 m h 100 m f 4.5 m h 2200 m fx2 2.67k 4.7k 10nf 1.5k 1nf 10nf 6.8k 1 2 3 4 5 6 7 8 10r 1n4148 2n7002 (12v) (3.3v) on/off q1 q2 q3 gate control oscillator digital soft-start power-on reset phase lgate fb gnd vcc boot ugate 50%v ref error amp pwm comparator u.v.p comparator sawtooth wave : 2 comp v ref f osc 200khz
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 0 f u n c t i o n d e s c r i p t i o n power-on-reset (por) the power-on-reset (por) function of APW7064 continually monitors the input supply voltage (v cc ) and the comp pin. the supply voltage (v cc ) must exceed its rising por threshold voltage. the por function initiates soft-start operation after vcc and comp voltages exceed their por thresholds. for operation with a single +12v power source, v i n and v cc are equivalent and the +12v power source must exceed the rising vcc threshold. the por function inhibits operation at disabled status ( v c o m p is less than 1.2v). with both input supplies above their por thresholds, the device initiates a soft-start interval. soft-start the APW7064 has a built-in digital soft-start to control the output voltage rise and limit the current surge during the start-up. in figure 1, when v cc exceeds rising por threshold voltage, it will delay 1024/fosc seconds and then begin soft-start. during soft-start, an internal ramp connected to the one of the positive inputs of the gm amplifier rises up from 0v to 2v to replace the reference voltage (1.2v) until the ramp voltage reaches the reference voltage. t h e s o f t - s t a r t i n t e r v a l i s d e c i d e d b y t h e o s c i l l a t o r f r e q u e n c y ( 2 0 0 k h z ) . t h e f o r m u l a t i o n i s g i v e n b y : figure 2. shows more detail of the fb voltage ramp. the fb voltage soft-start ramp is formed with many small steps of voltage. the voltage of one step is about 1 8 . 7 5 mv in v fb , and the period of one step is about 16/f osc . this method provides a controlled voltage rise and prevents the large peak current to charge output capacitor. f i g u r e 2 . t h e c o n t r o l l e d s t e p p e d f b v o l t a g e d u r i n g s o f t - s t a r t f i g u r e 1 . s o f t - s t a r t i n t e r v a l s h u t d o w n a n d e n a b l e p u l l i n g t h e c o m p v o l t a g e t o g n d b y a n o p e n d r a i n t r a n s i s t o r , s h o w n i n t y p i c a l a p p l i c a t i o n c i r c u i t , s h u t d o w n t h e a p w 7 0 6 4 p w m c o n t r o l l e r . i n s h u t d o w n m o d e , t h e u g a t e a n d l g a t e t u r n o f f a n d p u l l t o p h a s e a n d g n d r e s p e c t i v e l y . under voltage protection the fb pin is monitored during converter operation by the internal under voltage (uv) comparator. if the fb voltage drops below 50% of the reference voltage (50% of 1.2v = 0.6v), a fault signal is internally generated, and the device turns off both high-side and low-side mosfet and the converter?s output is latched to be floating. ms 1 . 5 1024/f t t t ms 1 . 5 /f 1024 t t t osc 2 3 start soft osc 1 2 delay = = - = = = - = - t 1 voltage (v) time v cc v out t 2 t 3 voltage (v) v fb 18.75 mv 16/f osc time
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 1 a p p l i c a t i o n i n f o r m a t i o n output voltage selection the output voltage can be programmed with a resistive divider. use 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier , and the reference voltage is 1.2v . the output voltage is determined by: where r out is the resistor connected from v out to fb and r gnd is the resistor connected from fb to gnd. output inductor selection the inductor value determines the inductor ripple current and affects the load transient response. higher inductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: where f s is the switching frequency of the regulator. although increase of the inductor value reduces the ripple current and voltage, a tradeoff will exist between the inductor?s ripple current and the regulator load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this will result in a larger output ripple voltage. output capacitor selection higher capacitor value and lower esr reduce the output ripple and the load transient drop. therefore, selecting high performance low esr capacitors is intended for switching regulator applications. in some applications, multiple capacitors have to be parallel to achieve the desired esr value. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. input capacitor selection the input capacitor is chosen based on the voltage rating and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out /2, where i out is the load current. during power up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. for high frequency decoupling, a ceramic capacitor 1 m f can be connected between the drain of upper mosfet and the source of lower mosfet. mosfet selection the selection of the n-channel power mosfets are determined by the r ds(on) , reverse transfer capacitance (c rss ) and maximum output current requirement. there are two components of loss in the mosfets: conduction loss and transition loss. for the upper and lower mosfet, the losses are approximately given by the following: ? ? ? ? ? + = gnd out out r r 1 2 . 1 v esr i v v v l f v v i ripple out in out s out in ripple = d - = where i out is the load current tc is the temperature dependency of r ds(on) f s is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction loss while the upper mosfet include an additional transition loss. the switching internal, t sw , is the function of the reverse trans- fer capacitance c rss . the (1+tc) term is to factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs tempera ture? curve of the power mosfet. d) - )(1 )(r t + (1 i = p )f t )( )(v i (0.5)( + )d )(r t + (1 i = p ds(on) c 2 out lower s sw in out ds(on) c 2 out upper
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 2 pwm compensation the output lc filter of a step down converter introduces a double pole, which contributes with -40db/decade gain slope and 180 degrees phase shift in the control loop. a compensation network among comp, fb, and v out should be added. the compensation network is shown in figure 6. the output lc filter consists of the output inductor and output capacitors. the transfer function of the lc filter is given by: a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) the poles and zero of this transfer functions are: the f lc is the double poles of the lc filter, and f esr is the zero introduced by the esr of the output capacitor. figure 3. the output lc filter the pwm modulator is shown in figure 5. the input is the output of the error amplifier and the output is the phase node. the transfer function of the pwm modulator is given by: figure 5. the pwm modulator figure 4. the lc filter gain and frequency v phase l v out c out esr output of error amplifier g v osc pwm comparator driver driver phase v in osc 1 c esr s c l s c esr s 1 gain out out 2 out lc + + + = out esr out lc c esr 2 1 f c l 2 1 f p = p = f lc f esr -40db/dec -20db/dec frequency(hz) g a i n ( d b ) osc in pwm v v gain d = the compensation network is shown in figure 6. it provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. the transfer function of error amplifier is given by: ( ) ? ? ? ? + ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? + + = ? ? ? ? + ? ? ? ? + = = c3 r3 1 s c2 c1 r2 c2 c1 s s c3 r3 r1 1 s c2 r2 1 s c1 r3 r1 r3 r1 sc3 1 r3 r1// sc2 1 r2 // sc1 1 v v gain out comp amp the poles and zeros of the transfer function are: ( ) c3 r3 2 1 f c2 c1 c2 c1 r2 2 1 f c3 r3 r1 2 1 f c2 r2 2 1 f p2 p1 z2 z1 p = ? ? ? ? + p = + p = p = figure 6. compensation network v ref v out v comp r 1 r 3 c 3 r 2 c 2 c 1 fb
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 3 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) the closed loop gain of the converter can be written as: pwm compensation (cont.) figure 7. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. using the below guidelines should give a compensation similar to the curve plotted. a stable closed loop has a -20db/ decade slope and a phase margin greater than 45 degree. 1.choose a value for r1, usually between 1k and 5k. 2.select the desired zero crossover frequency amp pwm lc gain x gain x gain use the following equation to calculate r2: esr o s o f > f > f x 1/10) ~ (1/5 : f calculate the c2 by the equation: r1 f f v v r2 lc o in osc d = 3.place the first zero f z1 before the output lc filter double pole frequency f lc . lc z1 f x 0.75 = f 0.75 f r2 2 1 c2 lc p = 4.set the pole at the esr zero frequency f esr : esr p1 f = f calculate the c1 by the equation: 1 f c2 r2 2 c2 c1 esr - p = 5.set the second pole f p2 at the half of the switching frequency and also set the second zero f z2 at the output lc filter double pole f lc . the compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at f p2 with the capabilities of the error amplifier. lc z2 s p2 f = f f x 0.5 = f combine the two equations will get the following component calculations: s lc s f r3 1 c3 1 f 2 f r1 r3 p = - = figure 7. converter gain and frequency f lc frequency(hz) g a i n ( d b ) 20log (r2/r1) 20log (v in / g v osc ) f z1 f z2 f p1 f p2 f esr pwm & filter gain converter gain compensation gain
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 4 l a y o u t c o n s i d e r a t i o n in any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. with power devices switching at 200khz,the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is free-wheeling by the lower mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short, wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. and signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a checklist for your layout: - keep the switching nodes (ugate, lgate, and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. - the traces from the gate drivers to the mosfets (ugate and lgate) should be short and wide. - place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close their pins. (for example, place the decoupling ceramic capacitor near the drain of the high-side mosfet as close as possible. the bulk capacitors are also placed near the drain). - the input capacitor should be near the drain of the upper mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. - the drain of the mosfets (v in and phase nodes) should be a large plane for heat sinking. figure 8. layout guidelines vcc boot phase ugate lgate v in v out l o a d APW7064
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 5 p a c k a g e i n f o r m a t i o n s o p - 8 p thermal pad d d1 e 2 e 1 e e b h x 4 5 o c see view a a 2 a a 1 view a l 0 . 2 5 gauge plane seating plane q note : 1. followed from jedec ms-012 ba. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. dimension "e" does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 0.020 0.010 0.020 0.050 0.006 0.063 max. 0.40 l 0 0 o c e e h e1 0.25 d c b 0.17 0.31 0.016 1.27 8 o c 0 o c 8 o c 0.50 1.27 bsc 0.51 0.25 0.050 bsc 0.010 0.012 0.007 millimeters min. s y m b o l a1 a2 a 0.00 1.25 sop-8p max. 0.15 1.60 min. 0.000 0.049 inches d1 2.50 0.098 2.00 0.079 e2 3.50 3.00 0.138 0.118 4.80 5.00 0.189 0.197 3.80 4.00 0.150 0.157 5.80 6.20 0.228 0.244
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 6 c a r r i e r t a p e & r e e l d i m e n s i o n s h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 so p - 8 p 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.4 0 6.40 ? 0.20 5.20 ? 0.20 2.10 ? 0.20 (mm) package type unit quantity sop - 8p tape & reel 2500 d e v i c e s p e r u n i t
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 7 t a p i n g d i r e c t i o n i n f o r m a t i o n s o p - 8 p c l a s s i f i c a t i o n p r o f i l e user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 8 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ 125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a115 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 0 9 a p w 7 0 6 4 w w w . a n p e c . c o m . t w 1 9 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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